1. Field of the Invention
This invention is related to the field of caching and, more particularly, to mechanisms for disabling a portion of a cache.
2. Description of the Related Art
Processors typically provide a set of registers which may be used by programs as a high speed, private storage for operands. The operands stored in registers may be frequently accessed variables, or may be intermediate results in a complex, multi-instruction calculation. Unfortunately, for many tasks, the number of registers provided in the processor may be too few to hold all of the operands of interest. In such cases, many of the frequently accessed variables and/or intermediate results are written to and read from memory locations during execution of the program.
The memory may have a significantly higher latency than the registers, limiting the speed at which the program may be executed as compared to the speed that may be achieved if all operands were in registers. Processors and/or the computer systems including the processors may provide caches to alleviate the memory latency. Generally, a cache is a relatively small, high speed memory which may store copies of data corresponding to various recently-accessed memory locations. Generally, cache storage is allocated and deallocated in units of cache lines (a group of bytes from contiguous memory locations). In other words, the cache may include multiple entries, and each entry may include storage for a cache line of bytes. If requested data for an access is not in the cache (a “miss”), an entry is allocated for the cache line including the requested data and the cache line is filled into the allocated entry. In some cases, a portion of the cache line (often called a “sector”) may be valid while other portions are invalid. However, the entire cache entry is allocated for the cache line if one or more of the sectors are valid.
While caches may reduce the average latency for memory accesses, the latency for any particular access is generally not deterministic. If the requested data is stored in the cache (a “hit”), then the latency is low. If the requested data is a miss in the cache, on the other hand, then the latency is high. Accesses may miss the cache for a variety of reasons. For example, an access misses the cache if the cache line including the requested data has not been accessed before. A current access may miss even if the cache line has been previously accessed, if other cache lines which map to the same entry (or set of entries, depending on the cache structure) are accessed in the interval between the previous access and the current access. In multi-master coherent environments, coherency activity due to accesses by other masters may cause cache lines to be invalidated in the cache. These various causes of cache misses may be hard to predict, and thus managing the cache to provide deterministic, low latency access to certain operands may be difficult to achieve. Accordingly, a mechanism for providing deterministic, low latency access to operands is desired.